Embodiments of the present invention relate to a computer system having a multi-node computer architecture. In particular, the present invention relates to a method and apparatus for invalidating cache lines in a multi-node architecture.
Computer systems may contain multiple processors that may work together to perform a task. For example, a computer system may contain four processors that may share system resources (e.g., input devices or memory devices) and may perform parallel processing. The processors may send messages to each other, may send messages to system resources, and may send and receive messages from the system resources. For example, such messages may include requests for information that is stored at a memory location in a memory device.
In many computer systems, the set of data currently being used by a microprocessor may be copied from a system memory device such as a dynamic random access memory (DRAM) into a relatively smaller but faster cache memory device such as a static random access memory (SRAM). The cache memory device is usually private to each processor such that only one processor can read or write to it. As would be appreciated by a person of skill in the art, a xe2x80x9ccache linexe2x80x9d is a single data entry in a cache memory device (xe2x80x9ccachexe2x80x9d). That is, a cache line may be the size of the data unit accessed in the cache, in which case the cache line corresponds to a particular block of data in a system memory (xe2x80x9cmemory blockxe2x80x9d). A cache line may be said to cache data for a particular memory block if the cache line contains the data element for that memory block. A memory block corresponds to a unit of system memory and may contain one or more data locations (e.g., 32 bytes). A processor may write to a memory block by writing to the corresponding cache line, in which case the cache line and the system memory may contain different values.
A cache is said to be xe2x80x9ccoherentxe2x80x9d if the information resident in the cache reflects a consistent view of the information in all the private cache memory devices and the system memory. If the cache has been updated without updating the system memory, then the system memory is said to contain xe2x80x9cstalexe2x80x9d data. Similarly, if the system memory has been updated without updating the cache, then the cache is said to contain xe2x80x9cstalexe2x80x9d data. As discussed above, a cache and a system memory do not always need to contain exact copies of one another. A cache line may be said to be in a xe2x80x9cmodifiedxe2x80x9d state if has been updated without updating the system memory. If a processor determines that a cache line contains stale data, the processor may xe2x80x9cinvalidatexe2x80x9d that cache line. In some systems, a cache line may be invalidated by setting a flag associated with that cache line to an invalid value. In such systems, when the cache line is invalidated, the cache controller does not use that cache line until a new data element is stored in the cache line.
A processor should not be allowed to use a stale copy of data. Cache xe2x80x9csnoopingxe2x80x9d is one technique used in some systems that have multiple processors to detect the state of a memory location in private cache memory devices on a memory access that might cause a cache coherency problem. Snooping may include the monitoring of a system bus by a first processor to determine if a second processor is accessing a block of system memory that is being cached in the first processor. If a system does not contain a shared bus, processors cannot snoop by monitoring a shared bus, and another method of preventing the use of stale data must be used.